1. Field of the Invention
The invention relates to a sample and hold circuit for holding an input voltage in response to a timing signal and outputting the holding voltage and, more particularly, to a sample and hold circuit which is suitable for use in a driving apparatus of an image display apparatus like a liquid crystal panel.
2. Related Background Art
A sample and hold circuit is used, for example, for a thin-film transistor driving circuit or the like of a liquid crystal panel. FIGS. 2(a) and 2(b) are circuit diagrams showing examples of constructions of conventional sample and hold circuits.
The sample and hold circuit shown in FIG. 2(a) is a circuit of the parallel 2-latch/1-buffer amplifier type disclosed in JP-B-6-54418 and has an input terminal 1 to which an input voltage IN is supplied and a control terminal 2 to which a switching signal SW is supplied. Capacitors 4a and 4b for holding the input voltage IN are connected to the input terminal 1 through transfer gates (hereinafter, also referred to as xe2x80x9cTGsxe2x80x9d) 3a and 3b, respectively. The capacitors 4a and 4b are connected to the input side of a buffer amplifier (hereinafter, also referred to as xe2x80x9cAMPxe2x80x9d) 6 having a voltage amplification factor 1 through TGs 5a and 5b, respectively. The output side of the AMP 6 is connected to an output terminal 7. The switching signal SW of the control terminal 2 is supplied as a control signal to the TGs 3a and 5b, inverted by an inverter 8, and supplied as a control signal to the TGs 3b and 5a. Each of the TGs 3b, 5a, and 5b has the same construction as that of the TG 3a. 
According to such a sample and hold circuit, when the switching signal SW is at the xe2x80x9cHxe2x80x9d level, the TGs 3a and 5b are turned on and the TGs 3b and 5a are turned off, so that the input voltage IN at the input terminal 1 is charged into the capacitor 4a through the TG 3a. On the other hand, a voltage charged in the capacitor 4b is supplied to the AMP 6 through the TG 5band outputted as an output voltage OUT from the AMP 6 to the output terminal 7.
Subsequently, when the switching signal SW is set to the xe2x80x9cLxe2x80x9d level, the TGs 3a and 5b are turned off and the TGs 3b and 5a are turned on, so that the input voltage IN at the input terminal 1 is charged into the capacitor 4b through the TG 3b. On the other hand, a voltage charged in the capacitor 4a is supplied to the AMP 6 through the TG 5a and outputted as an output voltage OUT from the AMP 6 to the output terminal 7.
As mentioned above, the input voltage IN is alternately charged into the two capacitors 4a and 4b in response to the switching signal SW and the charged voltage is outputted as an output voltage OUT through the AMP 6.
On the other hand, the sample and hold circuit shown in FIG. 2(b) is a circuit of the parallel 2-latch/2-buffer amplifier type disclosed in JP-A-11-249633 and constructed in a manner similar to that of FIG. 2(a) except that the AMP 6 at the post stage of the TGs 5a and 5b in FIG. 2(a) is deleted and AMPs 6a and 6b are provided between the capacitors 4a and 4b and the TGs 5a and 5b, respectively.
According to such a sample and hold circuit, when the switching signal SW is at the xe2x80x9cHxe2x80x9d level, the input voltage IN at the input terminal 1 is charged into the capacitor 4a through the TG 3a. On the other hand, the voltage charged in the capacitor 4b is supplied to the TG 5b through the AMP 6b and outputted as an output voltage OUT to the output terminal 7 through the TG 5b. 
Subsequently, when the switching signal SW is set to the xe2x80x9cLxe2x80x9d level, the input voltage IN at the input terminal 1 is charged into the capacitor 4b through the TG 3b. On the other hand, the voltage charged in the capacitor 4a is supplied to the TG 5a through the AMP 6a and outputted as an output voltage OUT to the output terminal 7 through the TG 5a. 
However, the conventional sample and hold circuits shown in FIGS. 2(a) and 2(b) have the following problems.
In the circuit of FIG. 2(a), since the amplifier for both capacitors 4a and 4b is used in common as an AMP 6, for example, when the switching signal SW is switched from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the TG 5a is turned on and the capacitor 4a is connected to the input side of the AMP 6. At this time, a parasitic capacitance on the input side of the AMP 6, that is, an electrostatic capacitance of a gate of an MOS transistor constructing a non-inverting input terminal of the AMP 6 has been charged to the same voltage as the output voltage OUT just before the switching. The electrostatic capacitance of the gate of the MOS transistor at each non-inverting input terminal which gives the parasitic capacitance is equal to about {fraction (1/10)} of that of each of the capacitors 4a and 4b. The input voltage of the AMP 6 is influenced by the charges charged in the parasitic capacitor, the initial voltage held in the capacitor 4a changes, and an error is caused in the input voltage of the AMP 6.
On the other hand, according to the circuit of FIG. 2(b), since the voltages which are applied to the capacitors 4a and 4b through the TGs 3a and 3b are simultaneously inputted to the dedicated AMPs 6a and 6b, the error which is caused in the parasitic capacitor due to the common use of the amplifier as in case of the circuit of FIG. 2(a) does not occur. However, since the two AMPs 6a and 6b are necessary, there is a problem of an increase in current consumption.
It is an object of the invention to provide a sample and hold circuit which does not cause an error due to a parasitic capacitance on the input side of an AMP and an increase in current consumption.
The invention is fundamentally made by paying attention to a construction in which an amplifier comprises: a differential input unit which generates a voltage according to a voltage difference between an input signal which is applied to a non-inverting input terminal and an input signal which is applied to an inverting input terminal; and a amplification output unit which amplifies an output voltage of the differential input unit. The invention is also based on an idea such that for the purpose of forming a pair of capacitors for holding an input voltage, a pair of differential input units are provided and a single amplification output unit which is shared by both of the differential input units is provided, thereby allowing the amplification output unit to alternately construct an amplifier together with both of the differential input units.
According to the first aspect of the invention, there is provided a sample and hold circuit comprising:
a pair of first switches whose operations are controlled by a switching signal and which alternately transfer input voltages to first and second nodes;
first and second capacitors which hold the input voltages transferred to the first and second nodes, respectively;
a first differential input unit which generates a voltage corresponding to a potential difference between the first node and an output terminal;
a second differential input unit which generates a voltage corresponding to a potential difference between the second node and the output terminal;
a pair of second switches which are controlled by the switching signal, transfer the voltage generated by the second differential input unit to a third node when the input voltage has been transferred to the first node, and transfer the voltage generated by the first differential input unit to the third node when the input voltage has been transferred to the second node; and
an output unit which outputs a voltage corresponding to the voltage at the third node to the output terminal.
The first and second differential input units have non-inverting input terminals and inverting input terminals. The non-inverting input terminals may be constructed by gates of field effect transistors. The non-inverting input terminals are connected to the first and second nodes, and an output of the output unit is fed back to the inverting input terminals, respectively.
For example, the output unit constructs a buffer amplifier together with each of the differential input units.
Each capacitor is, for example, a sample holding capacitor for holding a sampled image signal.
The first and second differential input units have, for example, field effect transistors each of which is serially connected to a single constant current circuit through the corresponding second switch, whose gates are connected to the corresponding first and second nodes, and which are mutually connected in parallel through the first and second switches.
Each of the first and second differential input units has an inverting input terminal to which an output of the output unit is fed back.
According to the second aspect of the invention, there is provided a sample and hold circuit comprising: a pair of switches which are controlled by a switching signal and transfer input voltages to first and second nodes; first and second capacitors which hold the input voltages transferred to the first and second nodes, respectively; and a buffer amplifier which is controlled by the switching signal, outputs the voltage held in the second capacitor to an output terminal when the input voltage has been transferred to the first node, and outputs the voltage held in the first capacitor to the output terminal when the input voltage has been transferred to the second node, wherein
the buffer amplifier comprises
a first non-inverting input unit having a first transistor which is on/off controlled by the switching signal and a second transistor which is serially connected to the first transistor and receives the voltage of the first capacitor and whose conducting state is controlled by this voltage,
a second non-inverting input unit which is connected to the first non-inverting input unit in parallel and has a third transistor which is on/off controlled by the switching signal in a complementary manner with the first transistor and a fourth transistor which is serially connected to the third transistor and receives the voltage of the second capacitor and whose conducting state is controlled by this voltage,
an inverting input unit which is connected to the first and second non-inverting input units in parallel and has a fifth transistor whose conducting state is controlled by the voltage at the output terminal,
a differential voltage generating unit which generates a voltage according to a difference between a current flowing in the first or second non-inverting input unit and a current flowing in the inverting input unit, and
an output unit having a sixth transistor whose conducting state is controlled by the voltage generated from the differential voltage generating unit and which outputs a voltage corresponding to the voltage of the first or second capacitor connected to the first or second non-inverting input unit controlled to an ON state by the switching signal to the output terminal.
In the buffer amplifier, for example, a transistor which is always set to the ON state is serially connected to the fifth transistor of the inverting input unit.
According to the third aspect of the invention, there is provided a sample and hold circuit for sequentially holding sampling voltages which are applied to an input terminal, comprising:
a pair of switches which are mutually connected to the input terminal in parallel and complementarily perform the switching operations;
a pair of capacitors which are selectively connected to the input terminal by each switch and sequentially and alternately hold the sampling voltages by the switching operation of each switch;
a pair of differential input units which are provided in correspondence to each of the capacitors and each of which has a non-inverting input terminal to which the sampling voltage held in the corresponding capacitor is applied, an inverting input terminal, and an output terminal which outputs an output voltage corresponding to a voltage difference between the inverting input terminal and the non-inverting input terminal; and
a single amplification output unit which has an input terminal which selectively and alternately receives the output voltages at the output terminals of both of the differential input units and an output terminal which amplifies the voltage that is applied to the input terminal and outputs the amplified voltage, and in which the output terminal voltages are fed back as feedback voltages to both of the inverting input terminals of the pair of differential input units, thereby alternately constructing a buffer amplifier in cooperation with each of the pair of differential input units.
Each of the non-inverting input terminals of the pair of differential input units is constructed by, for example, a gate of a field effect transistor.
The sampling voltage is an image signal for a display apparatus.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.